wolfSSL is a small, portable, embedded SSL/TLS library targeted for use by embedded systems developers. It is an open source implementation of TLS (SSL 3.0, TLS 1.0, 1.1, 1.2, 1.3, and DTLS 1.0, 1.2, and 1.3) written in the C programming language. It includes SSL/TLS client libraries and an SSL/TLS server implementation as well as support for multiple APIs, including those defined by SSL and TLS. wolfSSL also includes an OpenSSL compatibility interface with the most commonly used OpenSSL functions. wolfSSL – Embedded Communications Products
In February 2019, Daniel Stenberg, the creator of cURL, was hired by the wolfSSL project to work on cURL. Daniel Stenberg, founder and Chief Architect of cURL, joins wolfSSL
Protocol Notes:
wolfCrypt also includes support for the recent X25519 and Ed25519 algorithms.
wolfCrypt acts as a back-end crypto implementation for several popular software packages and libraries, including MIT Kerberos Kerberos: The Network Authentication Protocol (where it can be enabled using a build option).
+AES cipher modes !Device !AES-GCM !AES-CCM !AES-CBC !AES-ECB !AES-CTR | |||||
Intel AES-NI (Xeon and Core processor families) | All | All | All | All | All |
Freescale Cryptographic Accelerator and Assurance Module (CAAM) | All | All | All | All | |
Freescale Coldfire SEC (NXP MCF547X and MCF548X) | All | ||||
Freescale Kinetis MMCAU K50, K60, K70, and K80 (ARM Cortex-M4 core) | All | All | All | All | |
STMicroelectronics STM32 F1, F2, F4, L1, W Series (ARM Cortex - M3/M4) | All | All | |||
Cavium NITROX (III/V PX processors) | All | ||||
Microchip PIC32 MX/MZ (Embedded Connectivity) | All | All | All | ||
Texas Instruments TM4C1294 (ARM Cortex-M4F) | All | All | All | All | All |
Nordic NRF51 (Series SoC family, 32-bit ARM Cortex M0 processor core) | 128-bit | ||||
ARMv8 | All | All | All | ||
Intel QuickAssist Technology | All | All | |||
Freescale NXP LTC | All | All | All | All | All |
Xilinx Zynq UltraScale+ | 256-bit | ||||
Renesas RX65N (R5F565NEHDFB) | All | All | |||
Renesas RX72N (RTK5RX72N0C00000BJ) | All | All | |||
Renesas RX MPU (R5F571MLDDFC) | All | All | |||
Renesas Synergy DK-S7G2 | 128-bit |
- "All" denotes 128, 192, and 256-bit supported block sizes
+Triple DES cipher modes !Device !DES-CBC !DES-ECB !3DES-CBC | |||
Freescale Coldfire SEC (NXP MCF547X and MCF548X) | 64 bit | 192 bit | |
Freescale Kinetis MMCAU K50, K60, K70, and K80 (ARM Cortex-M4 core) | 64 bit | 192 bit | |
STMicroelectronics STM32 F1, F2, F4, L1, W Series (ARM Cortex - M3/M4) | 64 bit | 64 bit (encrypt) | 192 bit |
Cavium NITROX (III/V PX processors) | 192 bit | ||
Microchip PIC32 MX/MZ (Embedded Connectivity) | 64 bit | 192 bit | |
Texas Instruments TM4C1294 (ARM Cortex-M4F) | 64 bit | 192 bit |
+ !Device !RC4 !ChaCha20 | ||
AVX1/AVX2 (Intel and AMD x86) | Supported | |
Cavium NITROX (III/V PX processors) | 2048 bit max. |
+Hash function support !Device !MD5 !SHA1 !SHA2 !SHA-256 !SHA-384 !SHA-512 | ||||||
AVX1/AVX2 (Intel and AMD x86) | Supported | Supported | Supported | |||
Freescale Kinetis MMCAU K50, K60, K70, and K80 (ARM Cortex-M4 core) | Supported | Supported | Supported | |||
STMicroelectronics STM32 F1, F2, F4, L1, W Series (ARM Cortex - M3/M4) | Supported | Supported | ||||
Microchip PIC32 MX/MZ (Embedded Connectivity) | Supported | Supported | Supported | |||
ARMv8 | Supported | |||||
Intel QuickAssist Technology | Supported | Supported | Supported | |||
Freescale NXP LTC | Supported | Supported | ||||
Xilinx Zynq UltraScale+ | Supported | |||||
Renesas Synergy DK-S7G2 | Supported | Supported | ||||
Renesas RX65N (R5F565NEHDFB) | Supported | Supported | ||||
Renesas RX72N (RTK5RX72N0C00000BJ) | Supported | Supported | Supported | |||
Renesas RX MPU (R5F571MLDDFC) | Supported | Supported | Supported |
+Key operations: generation and exchange, elliptic curve cryptography !Device !RSA !ECC !ECC-DHE !X25519 !Ed25519 | |||||
Cavium NITROX (III/V PX processors) | 512–4096 bit | NIST Prime 192, 224, 256, 384, 521 | |||
Microchip/ Atmel ATECC508A (compatible with any MPU or MCU including: Atmel SMART and AVR MCUs) | 256 bit (NIST-P256) | ||||
Intel QuickAssist Technology | 512–4096 bit | 128, 256 bit | |||
Freescale NXP LTC | 512 - 4096 bit | 128, 256 bit | 128, 256 bit | 256 bit | 256 bit |
Xilinx Zynq UltraScale+ | 2048–4096 bit |
+MAC algorithms !Device !HMAC-MD5 !HMAC-SHA1 !HMAC-SHA2 !HMAC-SHA256 !SHA-3 !Poly1305 | ||||||
AVX1/AVX2 (Intel and AMD x86) | Supported | |||||
Cavium NITROX (III/V PX processors) | Supported | Supported | Supported | Supported | ||
Microchip PIC32 MX/MZ (Embedded Connectivity) | Supported | Supported | Supported | |||
Intel QuickAssist Technology | Supported | Supported | ||||
Renesas RX65N (R5F565NEHDFB) | Supported | Supported | ||||
Renesas RX72N (RTK5RX72N0C00000BJ) | ||||||
Renesas RX MPU (R5F571MLDDFC) | Supported | Supported | ||||
Renesas Synergy DK-S7G2 | Supported |
+Random number generation !Device !RNG | |
STMicroelectronics STM32 F1, F2, F4, L1, W Series (ARM Cortex - M3/M4) | Supported |
Cavium NITROX (III/V PX processors) | Supported |
Nordic NRF51 (Series SoC family, 32-bit ARM Cortex M0 processor core) | Supported |
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