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Serial presence detect

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In computing, serial presence detect ( SPD) is a standardized way to automatically access information about a memory module. Earlier 72-pin included five pins that provided five bits of parallel presence detect (PPD) data, but the 168-pin DIMM standard changed to a serial presence detect to encode more information.

When an ordinary modern computer is turned on, it starts by doing a power-on self-test (POST). Since about the mid-1990s, this process includes automatically configuring the hardware currently present. SPD is a memory hardware feature that makes it possible for the computer to know what memory is present, and what memory timings to use to access the memory.

Some computers adapt to hardware changes completely automatically. In most cases, there is a special optional procedure for accessing BIOS parameters, to view and potentially make changes in settings. It may be possible to control how the computer uses the memory SPD data—to choose settings, selectively modify memory timings, or possibly to completely override the SPD data (see overclocking).

Stored information

For a memory module to support SPD, the JEDEC standards require that certain parameters be in the lower 128 (or more, depending on the generation) bytes of an EEPROM located on the memory module. These bytes contain timing parameters, manufacturer, serial number and other useful information about the module. Devices utilizing the memory automatically determine key parameters of the module by reading this information. For example, the SPD data on an SDRAM module might provide information about the CAS latency so the system can set this correctly without user intervention.

The SPD EEPROM firmware is accessed using SMBus, a variant of the I²C protocol. This reduces the number of communication pins on the module to just two: a clock signal and a data signal. The EEPROM shares ground pins with the RAM, has its own power pin, and has three additional pins (SA0–2) to identify the slot, which are used to assign the EEPROM a unique address in the range 0x50–0x57. Not only can the communication lines be shared among 8 memory modules, the same SMBus is commonly used on motherboards for system health monitoring tasks such as reading power supply voltages, CPU temperatures, and fan speeds.

Before SPD, memory chips were spotted with parallel presence detect (PPD). PPD used a separate pin for each bit of information, which meant that only the speed and density of the memory module could be stored because of the limited space for pins.

SDR SDRAM

The first SPD specification was issued by JEDEC and tightened up by Intel as part of its PC100 memory specification introduced in 1998. Application note INN-8668-APN3: SDRAM SPD Data Standards, memorytesters.com Most values specified are in binary-coded decimal form. The most significant nibble can contain values from 10 to 15, and in some cases extends higher. In such cases, the encodings for 1, 2 and 3 are instead used to encode 16, 17 and 18. A most significant nibble of 0 is reserved to represent "undefined".

The SPD ROM defines up to three DRAM timings, for three CAS latencies specified by set bits in byte 18. First comes the highest CAS latency (fastest clock), then two lower CAS latencies with progressively lower clock speeds.

+ SPD contents for SDR SDRAM ! colspan=2	Byte ! colspan=8	Bit ! rowspan=2	Notes
Typically 128
Typically 8 (256 bytes)

Bank 2 is 0 if same as bank 1
Bank 2 is 0 if same as bank 1
Commonly 1 or 2
Commonly 64, or 72 for ECC DIMMs
0, unless width ≥ 256 bits
Decoded by table lookup
Clock cycle time at highest CAS latency
SDRAM access time from clock (t_AC)
Table lookup
Refresh requirements
Width of bank 1 data SDRAM devices. Bank 2 may be same width, or 2× width if bit 7 is set.
Width of bank 1 ECC/parity SDRAM devices. Bank 2 may be same width, or 2× width if bit 7 is set.
Typically 1
Burst lengths supported (bitmap)
Typically 2 or 4
latencies supported (bitmap)
latencies supported (bitmap)
latencies supported (bitmap)
Memory module feature bitmap
Memory chip feature support bitmap
Clock cycle time at medium CAS latency
Data access time from clock (t_AC)
Clock cycle time at short CAS latency.
Data access time from clock (t_AC)
Minimum row precharge time (t_RP)
Minimum row active–row active delay (t_RRD)
Minimum to delay (t_RCD)
Minimum active to precharge time (t_RAS)
Module bank density (bitmap). Two bits set if different size banks.
Address/command setup time from clock
Address/command hold time after clock
Data input setup time from clock
Data input hold time after clock
0x24–0x3d	colspan=8	For future standardization
SPD revision level; e.g., 1.2
Sum of bytes 0–62, not then negated
Stored little-endian, trailing zero-padded
Vendor-specific code
ASCII, space-padded
Vendor-specific code
Manufacturing date (YYWW)
Manufacturing date (YYWW)	Weeks (0–9)
Vendor-specific code
Could be enhanced performance profile
Intel frequency support
Intel feature bitmap

DDR SDRAM

The DDR DIMM SPD format is an extension of the SDR SDRAM format. Mostly, parameter ranges are rescaled to accommodate higher speeds.

+ SPD contents for DDR SDRAM ! colspan=2	Byte ! colspan=8	Bit ! rowspan=2	Notes
Typically 128
Typically 8 (256 bytes)

Bank 2 is 0 if same as bank 1.
Bank 2 is 0 if same as bank 1.
Commonly 1 or 2
Commonly 64, or 72 for ECC DIMMs
0, unless width ≥ 256 bits
Decoded by table lookup
Clock cycle time at highest CAS latency.
SDRAM access time from clock (t_AC)
Table lookup
Refresh requirements
Width of bank 1 data SDRAM devices. Bank 2 may be same width, or 2× width if bit 7 is set.
Width of bank 1 ECC/parity SDRAM devices. Bank 2 may be same width, or 2× width if bit 7 is set.
Typically 1
Burst lengths supported (bitmap)
Typically 4
latencies supported (bitmap)
latencies supported (bitmap)
latencies supported (bitmap)
Memory module feature bitmap
Memory chip feature bitmap
Clock cycle time at medium CAS latency.
Data access time from clock (t_AC)
Clock cycle time at short CAS latency.
Data access time from clock (t_AC)
Minimum row precharge time (t_RP)
Minimum row active–row active delay (t_RRD)
Minimum to delay (t_RCD)
Minimum active to precharge time (t_RAS)
Module bank density (bitmap). Two bits set if different size banks.
Address/command setup time from clock
Address/command hold time after clock
Data input setup time from clock
Data input hold time after clock
36–40	colspan=8	Superset information
Minimum active to active/refresh time (t_RC)
Minimum refresh to active/refresh time (t_RFC)
Maximum clock cycle time (t_CK max.)
Maximum skew, DQS to any DQ. (t_DQSQ max.)
Read data hold skew factor (t_QHS)
0x2e	colspan=8	For future standardization
Height of DIMM module, table lookup
0x30–0x3d	colspan=8	For future standardization
SPD revision level, 0.0 or 1.0
Sum of bytes 0–62, not then negated
Stored little-endian, trailing zero-padded
Vendor-specific code
ASCII, space-padded
Vendor-specific code
Manufacturing date (YYWW)
Manufacturing date (YYWW)	Weeks (0–9)
Vendor-specific code
Could be enhanced performance profile

DDR2 SDRAM

The DDR2 SPD standard makes a number of changes, but is roughly similar to the above. One notable deletion is the confusing and little-used support for DIMMs with two ranks of different sizes.

For cycle time fields (bytes 9, 23, 25 and 49), which are encoded in BCD, some additional encodings are defined for the tenths digit to represent some common timings exactly:

+ DDR2 BCD extensions ! Hex !! Binary !! Significance

0.25 ()

0.33 ()

0.66 ()

0.75 ()

0.875 (, Nvidia XMP extension)

+ SPD contents for DDR2 SDRAM
Typically 128
Typically 8 (256 bytes)



Commonly 0 or 1, meaning 1 or 2
Commonly 64, or 72 for ECC DIMMs

Decoded by table lookup. Commonly 5 = SSTL 1.8 V
Clock cycle time at highest CAS latency.
SDRAM access time from clock (t_AC)
Table lookup
Refresh requirements
Commonly 8 (module built from ×8 parts) or 16
Width of bank ECC/parity SDRAM devices. Commonly 0 or 8.

Burst lengths supported (bitmap)
Typically 4 or 8
latencies supported (bitmap)

DIMM type of this assembly (bitmap)
Memory module feature bitmap
Memory chip feature bitmap
Clock cycle time at medium CAS latency.
Data access time from clock (t_AC)
Clock cycle time at short CAS latency.
Data access time from clock (t_AC)
Minimum row precharge time (t_RP)
Minimum row active–row active delay (t_RRD)
Minimum to delay (t_RCD)
Minimum active to precharge time (t_RAS)
Size of each rank (bitmap).
Address/command setup time from clock
Address/command hold time after clock
Data input setup time from strobe
Data input hold time after strobe
Minimum write recovery time (t_WR)
Internal write to read command delay (t_WTR)
Internal read to precharge command delay (t_RTP)
Reserved for "memory analysis probe characteristics"
Extension of bytes 41 and 42.
Minimum active to active/refresh time (t_RC)
Minimum refresh to active/refresh time (t_RFC)
Maximum clock cycle time (t_CK max)
Maximum skew, DQS to any DQ. (t_DQSQ max)
Read data hold skew factor (t_QHS)
PLL relock time
For future standardization.
SPD revision level, usually 1.0
Sum of bytes 0–62, not negated
Stored little-endian, trailing zero-pad
Vendor-specific code
ASCII, space-padded (limited to (,-,), A–Z, a–z, 0–9, space)
Vendor-specific code
Manufacturing date (YYWW)
Manufacturing date (YYWW)	Weeks (1–52)
Vendor-specific code
Could be enhanced performance profile

DDR3 SDRAM

The DDR3 SDRAM standard significantly overhauls and simplifies the SPD contents layout. Instead of a number of BCD-encoded nanosecond fields, some "timebase" units are specified to high precision, and various timing parameters are encoded as multiples of that base unit. Further, the practice of specifying different time values depending on the CAS latency has been dropped; now there are just a single set of timing parameters.

Revision 1.1 lets some parameters be expressed as a "medium time base" value plus a (signed, −128 +127) "fine time base" correction. Generally, the medium time base is 1/8 ns (125 ps), and the fine time base is 1, 2.5 or 5 ps. For compatibility with earlier versions that lack the correction, the medium time base number is usually rounded up and the correction is negative. Values that work this way are:

+ DDR3 SPD two-part timing parameters ! MTB byte	Value
t_CKmin, minimum clock period
t_AAmin, minimum CAS latency time
t_RCDmin, minimum RAS# to CAS# delay
t_RPmin, minimum row precharge delay
t_RCmin, minimum active to active/precharge delay

+ SPD contents for DDR3 SDRAM JESD21-C Annex K: Serial Presence Detect for DDR3 SDRAM Modules, Release 4, SPD Revision 1.1, Release 6, SPD Revision 1.3

1.0, 1.1, 1.2 or 1.3
Type of RAM chips
Type of module; e.g., 2 = Unbuffered DIMM, 3 = SO-DIMM, 11=LRDIMM
Zero means 8 banks, 256 Mibit.

Modules voltages supported. 1.5 V is default.
Module organization
0x03 for 64-bit, non-ECC DIMM.
Fine Time Base, dividend/divisor
Medium Time Base, dividend/divisor; commonly 1/8
Medium Time Base, dividend/divisor; commonly 1/8	Divisor, nanoseconds (1–255)
In multiples of MTB

CAS latencies supported (bitmap)
CAS latencies supported (bitmap)	12
In multiples of MTB; e.g., 80/8 ns.
In multiples of MTB; e.g., 120/8 ns.
In multiples of MTB; e.g., 100/8 ns.
In multiples of MTB; e.g., 60/8 ns.
In multiples of MTB; e.g., 100/8 ns.
Upper 4 bits of bytes 23 and 22
In multiples of MTB; e.g., 280/8 ns.
In multiples of MTB; e.g., 396/8 ns.
In multiples of MTB; e.g., 1280/8 ns.
In multiples of MTB; e.g., 1280/8 ns.	Minimum refresh recovery delay, t_RFCmin, bits 15:8
In multiples of MTB; e.g., 60/8 ns.
In multiples of MTB; e.g., 60/8 ns.
In multiples of MTB; e.g., 240/8 ns.
In multiples of MTB; e.g., 240/8 ns.	Minimum four activate window delay t_FAWmin, bits 7:0
SDRAM optional features support bitmap
SDRAM thermal and refresh options
DIMM thermal sensor present?
Nonstandard SDRAM device type (e.g., stacked die)
Signed multiple of FTB, added to byte 12
Signed multiple of FTB, added to byte 16
Signed multiple of FTB, added to byte 18
Signed multiple of FTB, added to byte 20
Signed multiple of FTB, added to byte 23
For future standardization.
For row hammer mitigation
For future standardization.
Module nominal height
Module thickness, value = ceil(mm) − 1
JEDEC reference design used (11111=none)
Differs between registered/unbuffered
Assigned by JEP-106
Assigned by JEP-106	Module manufacturer ID, msbyte
Vendor-specific code
Manufacturing year (BCD)
Manufacturing week (BCD)
Vendor-specific code
Includes bytes 0–116 or 0–125; see byte 0 bit 7
ASCII subset, space-padded
Vendor-defined
As distinct from module manufacturer
Manufacturer-specific data
Available for customer use

The memory capacity of a module can be computed from bytes 4, 7 and 8. The module width (byte 8) divided by the number of bits per chip (byte 7) gives the number of chips per rank. That can then be multiplied by the per-chip capacity (byte 4) and the number of ranks of chips on the module (usually 1 or 2, from byte 7).

DDR4 SDRAM

The DDR4 SDRAM "Annex L" standard for SPD changes the EEPROM module used. Instead of the old AT24C02-compatible 256-byte EEPROMs, JEDEC now defines a new nonstandard EE1004 type with two pages at the SMBus level each with 256 bytes. The new memory still uses the old 0x50–0x57 addresses, but two additional address at 0x36 (SPA0) and 0x37 (SPA1) are now used to receive commands to select the currently-active page for the bus, a form of bank switching. Internally each logical page is further divided into two physical blocks of 128 bytes each, totaling four blocks and 512 bytes. Other semantics for "special" address ranges remain the same, although write protection is now addressed by blocks and a high voltage at SA0 is now required to change its status.

Annex L defines a few different layouts that can be plugged into a 512-byte (of which a maximum of 320 bytes are defined) template, depending on the type of the memory module. The bit definitions are similar to DDR3.

+ SPD contents for DDR4 SDRAM JESD21-C Annex L: Serial Presence Detect for DDR4 SDRAM Modules, Release 5
SPD bytes used
Typically 0x10, 0x11, 0x12
Type of RAM chips
Type of module; e.g., 2 = Unbuffered DIMM, 3 = SO-DIMM, 11=LRDIMM
Zero means no bank groups, 4 banks, 256 Mibit.

Signal loading
SDRAM optional features
SDRAM thermal and refresh options
Other SDRAM optional features
Secondary SDRAM package type
Module nominal voltage, VDD
Module organization
Module memory bus width in bits
Module thermal sensor
Extended base module type
colspan=8
Measured in ps.
In multiples of MTB; e.g., 100/8 ns.
In multiples of MTB; e.g., 60/8 ns.
CAS latencies supported bit-mask
CAS latencies supported bit-mask
CAS latencies supported bit-mask
CAS latencies supported bit-mask
In multiples of MTB; e.g., 1280/8 ns.
In multiples of MTB; e.g., 60/8 ns.
In multiples of MTB; e.g., 60/8 ns.
Upper nibbles for t_RASmin and t_RCmin
In multiples of MTB
In multiples of MTB
In multiples of MTB
In multiples of MTB
In multiples of MTB
In multiples of MTB
In multiples of MTB
In multiples of MTB
t_FAWmin most significant nibble
In multiples of MTB
In multiples of MTB
In multiples of MTB
In multiples of MTB
Upper nibble for t_WRmin
In multiples of MTB
Upper nibbles for t_WTRmin
In multiples of MTB
In multiples of MTB
Base configuration section
Connector to SDRAM bit mapping
Base configuration section
Two's complement multiplier for FTB units
Two's complement multiplier for FTB units
Two's complement multiplier for FTB units
Two's complement multiplier for FTB units
Two's complement multiplier for FTB units
Two's complement multiplier for FTB units
Two's complement multiplier for FTB units
Two's complement multiplier for FTB units
Two's complement multiplier for FTB units
CRC16 algorithm
CRC16 algorithm
Dependent upon memory module family (UDIMM, RDIMM, LRDIMM)
Hybrid memory architecture specific parameters
Extended function parameter block
See JEP-106
Manufacturer-defined manufacturing location code
Represented in Binary Coded Decimal (BCD)
Represented in Binary Coded Decimal (BCD)
Manufacturer-defined format for a unique serial number across part numbers
ASCII part number, unused digits should be set to 0x20
Manufacturer-defined revision code
See JEP-106
Manufacturer-defined stepping or 0xFF if not used
Manufacturer's specific data
colspan=8

DDR5 SDRAM

Preliminary table for DDR5, based on JESD400-5 specification.

DDR5 expands the SPD table to 1024-byte. SPD of DDR5 is using the I3C bus.

+ SPD contents for DDR5 SDRAM

EEPROM chip

There are three main generations of EEPROMs as described in JEDEC standards: the 256-byte EE1002 for DDR3 and earlier, the 512-byte EE1004 for DDR4, and the 1024-byte "hub" SPD1558 for DDR5. The EE1002 is the bog-standard 24-series EEPROM. The EE1004 is the newer 34-series EEPROM and differs mainly in having a "page switch" command to allow access to its full content (among other differences). The SPD1558 is very different.

There are also thermal sensor versions of EE1002 and EE1004 but they speak the same protocol for their SPD part.

Addressing

As mentioned above SPD uses three pins for addressing up to 8 separate modules from 0 to 7. This is only correct for EE1002 and EE1004; SPD1558 uses a single pin with grounding resistors to specify the module's identity from 0 to 7.SPD5118 Hub and Serial Presence Detect Device Standard JESD300-5B.01 Version 1.5.1 May 2023

For EE1002 and EE1004 the I²C address range is 0x50–0x57. They also use respond to 0x30–0x37 if they have not been write protected (see below). If they have an associated thermal sensor, they use 0x18–0x1F. All those values are seven-bit I²C addresses formed by a Device Type Identifier Code prefix (DTIC) with SA0-2: to read (1100) from slot 3, one uses '''110 0'''011 = 0x33. With a final R/W bit it forms the 8-bit Device Select Code. JEDEC Standard 21-C section 4.1.4 "Definition of the TSE2002av Serial Presence Detect (SPD) EEPROM with Temperature Sensor (TS) for Memory Module Applications"

The 5118 contains many devices. The hub itself lies at 0x50–0x57, as before. The local devices are addressed through the hub using I³C.

Write protection

The EE1002 has three layers of write protection. The hardware layer is in the form of a WC# pin; when driven low, it prevents all writes. The software layer is in the form of a few commands. Changing software write protect requires driving V_HV (instead of the regular 0 or 1 logic voltages) on the address pin SA0 with specific combinations for the other SA pins. As a result there is no differentaion of slot-id. The final layer is the "permanent" layer, a command that can be sent to render the first 128 bytes permanently unchangable.JEDEC Standard No. 21-C 4.1.3 Definition of the EE1002 and EE1002A Serial Presence Detect (SPD) EEPROMS 4_01_03R19-01.pdf

The EE1004 has no WC# pin or a "permanent" layer. It has four commands to separately set the write-protect status of each 64-byte slice of the device (using different ) and one to clear them all at once. These commands all require driving V_HV like before.JEDEC Standard No. 21-C 4.1.6 Definitions of the EE1004-v 4 Kbit Serial Presence Detect (SPD) EEPROM and TSE2004av 4 Kbit SPD EEPROM with Temperature Sensor (TS) for Memory Module Applications 4_01_06R26-01-1.pdf

The SPD5118 has two modes of protection. In the normal operating mode with the address pin connected to GND via a resistor, protection can only be added to 64-byte slices, not removed. In the "tester" mode with the address pin connected to GND directly however, these bits can be freely removed.

Extensions

The JEDEC standard only specifies some of the SPD bytes. The truly critical data (for up to DDR3) fits into the first 64 bytes, JEDEC Standard 21-C section 4.1.2.4 "SPDs for DDR SDRAM" JEDEC Standard 21-C section 4.1.2.10 "Specific SPDs for DDR2 SDRAM" JEDEC Standard 21-C section 4.1.2.11 "Serial Presence Detect (SPD) for DDR3 SDRAM Modules" JEDEC Standard 21-C section 4.1.2 "SERIAL PRESENCE DETECT STANDARD, General Standard" JEDEC Standard 21-C section 4.1.2.5 "Specific PDs for Synchronous DRAM (SDRAM)" while some of the remainder is earmarked for manufacturer identification. However, a 256-byte EEPROM is standardized (for up to DDR3). A number of uses have been made of the remaining space.

Memory generally comes with conservative timing recommendations in the SPD ROM, to ensure basic functionality on all systems. Enthusiasts often spend considerable time manually adjusting the memory timings for higher speed. Enabling special configurations such as Intel XMP or AMD EXPO often requires additional testing to ensure system stability and may void CPU warranty if used out of the manufacturer’s published specifications.

Enhanced Performance Profiles (EPP)

Enhanced Performance Profiles is an extension of SPD, developed by Nvidia and Corsair Gaming, which includes additional information for higher-performance operation of DDR2 SDRAM, including supply voltages and command timing information not included in the JEDEC SPD spec. The EPP information is stored in the same EEPROM, but in bytes 99–127, which are unused by standard DDR2 SPD.

+ EPP SPD ROM usage
EPP header
Profile AP1
Profile AP2
Profile AP3
Profile AP4

The parameters are particularly designed to fit the memory controller on the nForce 5, nForce 6 and nForce 7 chipsets. Nvidia encourages support for EPP in the BIOS for its high-end motherboard chipsets. This is intended to provide "one-click overclocking" to get better performance with minimal effort.

Nvidia's name for EPP memory that has been qualified for performance and stability is "SLI-ready memory". The term "SLI-ready-memory" has caused some confusion, as it has nothing to do with SLI video. One can use EPP/SLI memory with a single video card (even a non-Nvidia card), and one can run a multi-card SLI video setup without EPP/SLI memory.

An extended version, EPP 2.0, supports DDR3 memory as well. Enhanced Performance Profiles 2.0 (pp. 2–3)

Intel Extreme Memory Profile (XMP)

A similar, Intel-developed JEDEC SPD extension was developed for DDR3 SDRAM DIMMs, later used in DDR4 and DDR5 SDRAM as well. XMP uses bytes 176–255, which are unallocated by JEDEC, to encode higher-performance memory timings.

Later, AMD developed AMP, an equivalent technology to XMP, for use in its "Radeon Memory" line of memory modules optimized for use in AMD platforms. Furthermore, motherboard developers implemented their own technologies to allow their AMD-based motherboards to read XMP profiles: MSI offers A-XMP, ASUS has DOCP (Direct Over Clock Profile), and Gigabyte has EOCP (Extended Over Clock Profile).

DDR3 XMP

+ XMP SPD ROM usage

XMP header

XMP profile 1 ("enthusiast" settings)

XMP profile 2 ("extreme" settings)

The header contains the following data. Most importantly, it contains a "medium timebase" value MTB, as a rational number of nanoseconds (common values are 1/8, 1/12 and 1/16 ns). Many other later timing values are expressed as an integer number of MTB units.

Also included in the header is the number of DIMMs per memory channel that the profile is designed to support; including more DIMMs may not work well.

+ XMP Header bytes

XMP magic number byte 1 0x0C

XMP magic number byte 2 0x4A

Profile 1 enabled (if 0, disabled)

Profile 2 enabled

Profile 1 DIMMs per channel (1–4 encoded as 0–3)

Profile 2 DIMMs per channel

XMP minor version number (x.0 or x.1)

XMP major version number (0.x or 1.x)

Medium timebase dividend for profile 1

Medium timebase divisor for profile 1 (MTB = dividend/divisor ns)

Medium timebase dividend for profile 2 (e.g. 8)

Medium timebase divisor for profile 2 (e.g. 1, giving MTB = 1/8 ns)

+ XMP profile bytes

Module Vdd voltage twentieths (0.00 or 0.05)

Module Vdd voltage tenths (0.0–0.9)

Module Vdd voltage units (0–2)

Minimum SDRAM clock period t_CKmin (MTB units)

Minimum CAS latency time t_AAmin (MTB units)

CAS latencies supported (bitmap, 4–11 encoded as bits 0–7)

CAS latencies supported (bitmap, 12–18 encoded as bits 0–6)

Minimum CAS write latency time t_CWLmin (MTB units)

Minimum row precharge delay time t_RPmin (MTB units)

Minimum RAS to CAS delay time t_RCDmin (MTB units)

Minimum write recovery time t_WRmin (MTB units)

t_RASmin upper nibble (bits 11:8)

t_RCmin upper nibble (bits 11:8)

Minimum active to precharge delay time t_RASmin bits 7:0 (MTB units)

Minimum active to active/refresh delay time t_RCmin bits 7:0 (MTB units)

Maximum average refresh interval t_REFI lsbyte (MTB units)

Maximum average refresh interval t_REFI msbyte (MTB units)

Minimum refresh recovery delay time t_RFCmin lsbyte (MTB units)

Minimum refresh recovery delay time t_RFCmin msbyte (MTB units)

Minimum internal read to precharge command delay time t_RTPmin (MTB units)

Minimum row active to row active delay time t_RRDmin (MTB units)

t_FAWmin upper nibble (bits 11:8)

Minimum four activate window delay time t_FAWmin bits 7:0 (MTB units)

Minimum internal write to read command delay time t_WTRmin (MTB units)

Write to read command turnaround time adjustment (0–7 clock cycles)

Write to read command turnaround adjustment sign (0=pull-in, 1=push-out)

Read to write command turnaround time adjustment (0–7 clock cycles)

Read to write command turnaround adjustment sign (0=pull-in, 1=push-out)

Back-to-back command turnaround time adjustment (0–7 clock cycles)

Back-to-back turnaround adjustment sign (0=pull-in, 1=push-out)

System CMD rate mode. 0=JTAG default, otherwise in peculiar units of MTB × t_CK/ns.
E.g. if MTB is 1/8 ns, then this is in units of 1/8 clock cycle.

SDRAM auto self refresh performance.
Standard version 1.1 says documentation is .

Reserved, vendor-specific personality code.

Newer versions

DDR4 specs are not yet publicly available.

AMD Extended Profiles for Overclocking (EXPO)

AMD's Extended Profiles for Overclocking (EXPO) is a JEDEC SPD extension developed for DDR5 DIMMs to apply a one-click automatic overclocking profile to system memory. AMD EXPO-certified DIMMs include optimised timings certified to work on Zen 4 processors. Unlike Intel's closed standard XMP, the EXPO standard is open and royalty-free. It can be used on Intel platforms. At launch in September 2022, there are 15 partner RAM kits with EXPO-certification available reaching up to 6400 MT/s.

Vendor-specific memory

A common misuse is to write information to certain memory regions to bind vendor-specific memory modules to a specific system. Fujitsu Technology Solutions is known to do this. Adding different memory module to the system usually results in a refusal or other counter-measures (like pressing F1 on every boot).

02 0E 00 01-00 00 00 EF-02 03 19 4D-BC 47 C3 46 ...........M.G.F
53 43 00 04-EF 4F 8D 1F-00 01 70 00-01 03 C1 CF SC...O....p.....

This is the output of a 512 MB memory module from Micron Technologies, branded for Fujitsu-Siemens Computers, note the "FSC" (46 53 43) string. The system BIOS rejects memory modules that don't have this information starting at offset 128h.

Some Packard Bell AMD laptops also use this method, in this case the symptoms can vary but it can lead to a flashing cursor rather than a beep pattern. Incidentally this can also be a symptom of BIOS corruption as well. Though upgrading a 2 GB to a 4 GB can also lead to issues.

Reading and writing SPD information

Memory module manufacturers write the SPD information to the EEPROM on the module. Motherboard read the SPD information to configure the memory controller.

Onboard SMBus

The motherboard SMBus controller is the "raw" way of accessing SPD on a memory module attached to it. Some motherboard chipsets allow selecting whether the SPD should be write protected. To allow access this way, the operating system must include SMBus support, have appropriate drivers for the EEPROMs, and the motherboard SMBus needs to be connected to the SPD EEPROMs.

(R) On Linux and FreeBSD, the userspace program provided by decodes and prints JEDEC standard information on any memory with SPD information in the computer. It requires the pre-DDR4 SPD it requires either the "eeprom" or the "at24" driver (24-series EEPROM). For DDR4 SPD it requires either the "eeprom" driver or the "ee1004" driver (34-series EEPROMs defined in JEDEC EE1004). On older Linux distributions, decode-dimms.pl was available as part of lm_sensors.

(W) The tool from i2c-tools allows writing to 24-series EEPROMs, i.e. up to DDR3.

(RW) On Linux and FreeBSD, the Python script reads and writes AT24 and EE1004-series EEPROMs. It only provides raw SMBus reading and writing, not decoding. Driver requirements are the same as .
(R) On OpenBSD 4.3+ and NetBSD 5.0+, the spdmem(4) driver accesses the EEPROM through the SMBus to provide information about memory modules (only the JEDEC standard part).
(R) Coreboot reads and uses SPD information to initialize all memory controllers in a computer with timing, size and other properties. Coreboot is intended to act as a computer's firmware, replacing a BIOS (or UEFI-enabled BIOS).
(R) HWiNFO, CPU-Z and Speccy are Microsoft Windows programs that read and display SPD information, including XMP and other extensions.
(RW) Thaiphoon Burner (abandonware) is a Windows program that allows reading from and writing to SPD from memory modules up to DDR4 (including XMP). SPDtool is another piece of abandonware of similar purpose.

Other SMBus features

Temperature sensor

JEDEC has standards for SMBus-addressable temperature sensors on memory strips. TS3000 is for the independent sensor for up to DDR3. TSE2002 is the combined SPD and temperature sensor for up to DDR3. TSE2004 is the combined SPD and temperature sensor for DDR4. SPD5118 is the "hub" that integrates temperature and SPD on DDR5.

RGB LED control

Some memory modules (especially on ) support RGB LEDs that are controlled by proprietary SMBus commands. This allows LED color control without additional connectors and cables. Windows kernel drivers from multiple manufacturers required to control the lights have been exploited to gain access ranging from full kernel memory access, to MSR and I/O port control numerous times in 2020 alone.

SMBIOS

The SMBIOS relays data about the memory from the BIOS to the computer. This information is accessed by the dmidecode program, which runs on Linux, FreeBSD, NetBSD, OpenBSD, BeOS, Cygwin and Solaris. Again, it accesses not the SPD information, but SMBIOS information, so data may be limited or incorrect.

Ex situ SMBus

By removing the EEPROM chip and transplanting it somewhere else, one can obtain a more direct SMBus access. This helps remove the interference from chipsets.

Laptops and webcams

A not so common use for old laptops is as generic SMBus readers, as the internal EEPROM on the module can be disabled once the BIOS has read it so the bus is essentially available for use. The method used is to pull low the A0,A1 lines so the internal memory shuts down, allowing the external device to access the SMBus. Once this is done, a custom Linux build or DOS application can then access the external device. A common use is recovering data from LCD panel memory chips to retrofit a generic panel into a proprietary laptop.

A related technique is rewriting the chip on webcams often included with many laptops, as the bus speed is substantially higher. They can even be modified so that 25-series chips, commonly used in storing a motherboard's UEFI ROM, can be read and written for protection against chip failure.

On some chips it is also a good idea to separate write protect lines so that the onboard chips do not get wiped during reprogramming.

Chip generation issues

This unfortunately only works on DDR3 and below, as DDR4 uses a different chip model (34-series) to fit the 512-byte SPD (as opposed to the 256-byte of earlier generations). This chip interface (EE1004/TSE2004) divides its storage into two pages and requires a page-switch to read or write the whole chip.

Some chipsets also do not correctly negotiate the reading of 34-series EEPROM chips so they may even fail to read. The software may return a "Incompatible SMBus driver?" message in response.

DDR5 uses an even more complex design, the SPD5118 "hub" with another doubling of capacity.

On older equipment

Some older equipment require the use of with parallel presence detect (more commonly called simply presence detect or PD). Some of this equipment uses non-standard PD coding, IBM computers and Hewlett-Packard LaserJet and other printers in particular.

Serial presence detect

( Computer Memory )

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Serial presence detect ( Computer Memory )

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Serial presence detect

( Computer Memory )